Semiconductor memory devices include, for example, static random access memory (SRAM) and dynamic random access memory (DRAM). A DRAM cell generally includes one transistor and one capacitor. The capacitor can be either charged or discharged to store information as a corresponding bit value (e.g., 0 or 1). Because capacitors leak charge, the stored information eventually fades unless the capacitor charge is refreshed periodically. Due to the refresh requirement, DRAM is referred to as dynamic memory as opposed to SRAM and other static memory.
DRAM scaling continues to increase the total number of bits (or cells) for each DRAM chip (or die), directly impacting the specification of DRAM refresh operations, the process by which a cell's value is kept readable. The specification of DRAM refresh operations includes, for DRAM dies operating in a controller-managed refresh mode whereby refreshes of the DRAM die are controlled by a controller that is external to the DRAM die, the interval at which refresh commands are sent to each DRAM die (tREF) and the amount of time that the refresh command occupies the DRAM interface and the DRAM die conducts the refresh (tRFC). Unfortunately, DRAM scaling increases the number of weak retention rows (e.g., rows that have at least one cell that has a reduced retention time). Such rows involve additional refresh cycles to maintain the stored information. A significant performance and power consumption impact is caused by the increased refresh cycles in a system on chip (SoC) or other like computer architecture. Otherwise, potential DRAM chip (or die) yield loss results without increased refresh cycles.